Direct memory access (DMA) controllers are heavily utilized in the field of digital signal processing (DSP). Such controllers can provide enhanced system performance by off loading the task of real-time data transactions from the central processing unit (CPU). The transfer controller with hub and ports architecture (TCHP) described in U.K. Patent Application No. 9901996.9 filed Apr. 10, 1999 entitled TRANSFER CONTROLLER WITH HUB AND PORTS ARCHITECTURE, having a convention application now U.S. Pat. No. 6,496,740, provides flexibility and performance above and beyond that of previous DMA implementations through increased parallelism, pipelining, and improved hardware architecture.
Despite their flexibility and improved system performance, all DMA controllers face a common problem. Because DMAs are fundamentally architected to perform memory transactions, the sharing of any addressable resource with another controller poses a significant challenge to system design. Historically, this has been addressed either by multiple porting of such addressable resources, or through arbitration schemes, ranging from the very simple to the very complex.
Multiple porting of memory is the simplest method of supporting access by two or more bus masters, such as a DMA controller and a CPU. While simple, the cost paid for such porting is both physical area, as multi-ported memories are larger than their equivalent single-ported counterparts, and performance, as such porting enforces increased latency on accesses, thus reducing the maximum access rate.
Arbitration for a single-ported addressable resource also has its pitfalls. If the number of masters in the system becomes very large, the arbitration scheme will typically become either very complex or very inefficient. Furthermore, with a large number of requesters of a resource, requesters on the lowest of the prioritization levels may often be blocked out for long periods of time trying to gain access to the resource.
At the direct memory access (DMA) level, there are additional challenges in supporting sharing of resources with a mastering peripheral. Since the DMA typically wishes to master its own accesses, peripherals may not freely push data into or out of the DMA or addressable resources that the DMA accesses. To account for delays in arbitration that may be present, such peripherals often must incur an overhead of buffering, and often a complex handshaking scheme must be adopted to ensure that no data is lost.
To further complicate matters, it is often necessary to verify many boundary conditions to ensure that various memory ports and peripherals do not get into a state of lockup. A classic example of this is when a peripheral tries to push data out of its boundary and into a destination, while at the same time the destination is being read by the DMA. Since the read by the DMA cannot complete, the interface must stall. However, if the interface stalls the reads will never complete and thus the system locks up.
One approach to such issues that has been implemented in various DMA designs has been the inclusion of a separate port for mastering controllers, which allows the controller to directly access registers of the addressing machines of the DMA. Including such a port greatly reduces the complexity of the system, because once the addressing machines of the DMA are loaded, the accesses performed look like any other DMA access. Hence, whatever arbitration scheme exists within the DMA or for shared resources outside of the DMA (for example, between the DMA and a CPU) will suffice for this access type as well. Thus, support for access to addressable resources by a controller other than the DMA can be provided without having to add additional ports or arbitration to each resource.
The early direct memory access has evolved into several successive versions of centralized transfer controllers and more recently into the transfer controller with hub and ports architecture. The transfer controller with hub and ports architecture is described in U.K. Patent Application No. 9901996.9 filed Apr. 10, 1999 entitled TRANSFER CONTROLLER WITH HUB AND PORTS ARCHITECTURE, having a convention application now U.S. Pat. No. 6,496,740.
A first transfer controller module was developed for the TMS320C80 digital signal processor from Texas Instruments. The transfer controller consolidated the direct memory access function of a conventional controller along with the address generation logic required for servicing cache and long distance data transfer, also called direct external access, from four digital signal processors and a single RISC (reduced instruction set computer) processor.
The transfer controller architecture of the TMS320C80 is fundamentally different from a direct memory access in that only a single set of address generation and parameter registers is required. Prior direct memory access units required multiple sets for multiple channels. The single set of registers, however, can be utilized by all direct memory access requesters. Direct memory access requests are posted to the transfer controller via set of encoded inputs at the periphery of the device. Additionally, each of the digital signal processors can submit requests to the transfer controller. The external encoded inputs are called “externally initiated packet transfers” (XPTs). The digital signal processor initiated transfers are referred to as “packet transfers” (PTs). The RISC processor could also submit packet transfer requests to the transfer controller.
The transfer controller with hub and ports introduced several new concepts. The first was uniform pipelining. New digital signal processor devices containing a transfer controller with hub and ports architecture have multiple external ports, all of which look identical to the hub. Thus peripherals and memory may be freely interchanged without affecting the hub. The second new idea is the concept of concurrent execution of transfers. That is, up to N transfers may occur in parallel on the multiple ports of the device, where N is the number of channels in the transfer controller with hub and ports core. Each channel in the transfer controller with hub and ports core is functionally just a set of registers. This set of registers tracks the current source and destination addresses, the word counts and other parameters for the transfer. Each channel is identical, and thus the number of channels supported by the transfer controller with hub and ports is highly scalable.
Finally the transfer controller with hub and ports includes a mechanism for queuing transfers up in a dedicated queue memory. The TMS320C80 transfer controller permitted only was one transfer outstanding per processor at a time. Through the queue memory provided by the transfer controller with hub and ports, processors may issue numerous transfer requests up to the queue memory size before stalling the digital signal processor.
The present invention deals with the data transfer connecting various memory port nodes as applied to the transfer controller with hub and ports, which is the subject of U.K. Patent Application No. 9909196.9 filed Apr. 10, 1999, having a convention application now U.S. Pat. No. 6,496,740. The transfer controller with hub and ports is a significant basic improvement in data transfer techniques in complex digital systems and provides many useful features, one of which is the internal memory port which allows connection of a virtually unlimited number of processor/memory nodes to a centralized transfer controller. The centralized transfer controller must be able to transfer data from node to node with performance relatively independent of how near or remote a node might be from the transfer controller itself. To clarify the problem solved by the present invention, it is helpful to review the characteristics, architecture, and functional building blocks of the transfer controller with hub and ports.